The present invention, in one aspect thereof, relates to techniques for manufacturing and testing a semiconductor integrated circuit device, and more particularly to techniques which are effective for enhancing a productivity in the development of a large-scale logic integrated circuit device.
In the developments of, for example, a general purpose electronic computer system and a large-scale logic integrated circuit device for use in the system, it is actually difficult to fabricate the large-scale logic integrated circuit device having errorless perfect logical functions at the stage which precedes the assemblage of the circuit device into the system. Further, the corrections of the logical functions of the circuit device become indispensable due to the alteration of the specification of the system, or the like.
Therefore, the following methods are considered for coping with the logical defects of the large-scale logic integrated circuit device found out after the assemblage of the actual system and the corrections of the logical functions requested on the basis of the specification alteration or the like:
The request for the corrections of the logical functions is coped with by changing a mask pattern relative to wiring in accordance with a so-called master slice system wherein a large-scale logic integrated circuit device having desired logical functions is obtained merely by adding the design of the wiring among basic cells to a semiconductor wafer in the state in which the formation of the basic cells has been completed.
Besides, a test after the logic corrections is usually conducted for the large-scale logic integrated circuit device held in the wafer state, by the use of a so-called wafer prober.
By the way, techniques for manufacturing the large-scale logic integrated circuit device in accordance with the master slice system are contained in xe2x80x9cLSI HANDBOOKxe2x80x9d, p. 204-p. 205, edited by the Japan Society of Electronics and Communications, issued on Nov. 30, 1984 by the Ohm-Sha, Ltd.
Also, techniques for testing the semiconductor integrated circuit device in a chip state with the wafer prober are contained in the official gazette of Japanese Patent Application Laid-Open No. 116144/1985.
As a second aspect of the present invention, this aspect relates to a cutting depth controlling technique used in applying a cutting work to an LSI on a mask for exposure, using a focused ion beam or the like.
This second aspect of the present invention also relates to a cutting technique of a high accuracy which is carried out under radiation of an ion beam, and particularly to a technique of cutting with a high accuracy an internal layer of, for example, an LSI having a multilayer structure.
This second aspect of the present invention further relates to a semiconductor device and a cutting technique using an ion beam for making same, and particularly to a technique effective in its application to cutting and exposure of wiring using an ion beam to effect logical correction in a logical element, take measures against a defective design or make analysis of a defect.
Further, this second aspect of the present invention relates to a semiconductor integrated circuit device and particularly to a technique effective in its application to the analysis of defects.
Further, this second aspect of the present invention relates to a cutting depth monitoring technique in cutting an LSI or a mask for exposure using a focused ion beam or the like.
In an LSI developing process it has recently become very important to make debugging, correction or analysis of a defect by cutting or connecting a part of a wiring in an LSI chip To this end, there have heretofore been reported examples of cutting a wiring in an LSI chip using a focused ion beam.
For example, Japanese Patent Laid-Open No. 106750/83 (Focused Ion Beam Cutting Method) describes that it is possible to effect cutting at different etching depths by changing the dose amount, radiation time and acceleration voltage of an ion beam.
Further, as a technique associated with a higher integration of a semiconductor device such as an LSI (large scale integrated circuit) and shortening of the developing period, a technique of cutting a wiring of the LSI by radiating a focused ion beam to a predetermined cutting region with a view to making debugging, correction or analysis of a defect of the LSI is disclosed in detail, for example, in the foregoing Japanese Patent Laid-Open No. 106750/83, which technique is outlined as follows. In etching a workpiece selectively by radiating a focused ion beam thereto, desired etching depths for the workpiece are preset as positional functions and on the basis of the preset data the ion beam is radiated while changing the dose amount and radiation time of the beam as well as acceleration voltage, whereby it is intended to effect etching at different depths. The above patent publication fully describes an etching control in the depth direction, but as to positioning of the cutting region in the planar direction, the said publication merely states that an ion beam is radiated to a part to be cut while referring to a positioning mark formed on the workpiece.
Further, as a cutting technique using an ion beam in the production of a semiconductor device, there is known the technique disclosed in Japanese Patent Laid-Open No. 202038/83. According to an outline of this technique, there is provided an end point detecting means for detecting a cutting end point accurately by observing charged particles such as secondary ions or secondary electrons or an emission spectrum emitted from an ion beam-radiated part of a workpiece during cutting, whereby in removing a black spot defect caused by the adhesion of a light shielding film such as a chromium film to a part which should be transparent, for example, in a photo mask, it is intended to prevent a glass substrate located below the black spot defect from being damaged by excess cutting.
Further, according to a conventional technique for measuring the potential of a defective part of an internal circuit in the analysis of a defect of an IC (integrated circuit) or an LSI, a laser beam is applied to an insulation film on an aluminum wiring of the defective part to form a hole and probes are manually put on the surface of the wiring (e.g., Japanese Patent Publication No. 6173/79).
The present invention, in a third aspect thereof, relates to a technique which may be effectively applied to a semiconductor integrated circuit device having a multilayer wiring structure and a process for producing such a semiconductor integrated circuit device.
Recently, it has been increasingly important to develop an effective technique of repairing a defective part in an LSI (Large Scale Integrated Circuit) or changing a logical design thereof by disconnecting and properly reconnecting part of the wirings within the LSI circuit after the completion of the LSI which is still in the form of a wafer or chip.
To attain the above-described object, proposed in Japanese Patent Application No. 70979/1986 was a method of connecting wirings in an LSI by a combination of an ion beam technique and a laser CVD technique. According to the proposed method, after the completion of an LSI having, for example, a double-layer wiring structure, wirings in a first-level layer are interconnected for the purpose, for example, of repairing a defective part or changing a logical design. In this case, since the wiring in the uppermost layer is generally widely laid out in order to supply a power supply current, it is necessary to provide contact holes extending through the wiring in the uppermost-level layer so as to reach the wirings in the lower-level layers and also provide a connecting wiring through the contact holes. For this arrangement, an insulating film on the uppermost-level wiring layer, the second-level wiring layer and an intermediate insulating film between the second-level wiring layer and the first-level wiring layer are processed by irradiation with a focused ion beam to form contact holes, thereby partially exposing the surfaces of the wirings in the first-level layer through the contact holes. After an insulating film, e.g., a silicon dioxide (SiO2) film, has been formed on the whole surface of the chip, this insulating film is patterned by the use of photolithography and etching techniques so that the insulating film is left only in the vicinities of the contact holes. Then, the insulating film on the bottoms of the contact holes are removed by selective etching so that the surfaces of the wirings in the first-level layer are partially exposed through the contact holes again. Then, a metal is selectively deposited by laser CVD to thereby form a connecting wiring which interconnects the wirings in the first-level layer through the contact holes. In this case, since the connecting wiring is insulated from the wiring in the second-level layer by the insulating films formed within the contact holes, the wirings in the first- and second-level layers are prevented from shorting to each other.
On the other hand, as the result of increases in the degree of integration and miniaturization of ICs, it has recently been increasingly important to conduct an operation in which a defective part of an LSI is debugged or repaired in the step of developing the same by disconnecting and properly reconnecting part of the wirings within the LSI chip, thereby detecting errors in design or process, carrying out a defect analysis and returning the LSI to the process conditions, and thus increasing the production yield. For this purpose, examples in which the wirings in ICs are disconnected by means of a laser or ion beam have heretofore been reported.
More specifically, as a first prior art, xe2x80x9cLaser Stripe Cutting System for IC Debuggingxe2x80x9d (Tech Digest of CLEO"" 81, 1981, p. 160) is known. In this prior art, an example in which wirings are disconnected by means of a laser to debug a defective part is reported. As a second prior art, Japanese Patent Application No. 42126/1983 is known. This prior art discloses a technique in which an ion beam generated from a liquid metal ion source is focused in the shape of a spot having a diameter of 0.5 m, or less to disconnect wirings and bore holes and a metal is deposited in the holes by an ion beam to thereby interconnect the upper and lower wirings.
As a third prior art, xe2x80x9cDirect Writing of Highly Conductive Mo Lines by Laser Induced CVDxe2x80x9d (Extended Abstruct of 17th Conf. on Solid State Devices and Material, 1985, p. 193) is known.
In a fourth aspect, the present invention relates to techniques which are effective for correcting the connections of wirings by using the laser CVD technique and the focused ion beam technique.
A logic MIS, such as a microprocessor or a gate array, frequently has its logic structures corrected (logic corrections) during its development. This logic correction is accomplished by altering the pattern of the wirings connecting the logic gates.
However, the logic correction would elongate the development period of the LSI if it were started by altering the wiring mask pattern. Thus, as a method of correcting the wiring connections, there has been practiced the technique combining the focused ion beam (FIB) and the laser CVD.
In this technique, the passivation film of an integrated circuit formed over a semiconductor wafer (which will be shortly referred to as xe2x80x9cwaferxe2x80x9d) is etched with a focused ion beam to expose the wiring to-be-cut to the outside. After this wiring is cut with the focused ion beam, a conductive pattern of molybdenum (Mo) or tungsten (W) is selectively deposited with the laser CVD between the predetermined preliminary wiring and the logic gate.
The focused ion beam can have its ion beam focused to a spot size of about 0.1 xcexcm and is advantageous in that it can cut and process a fine wiring at high precision. Here, the focused ion beam technique is disclosed, for example, in xe2x80x9cElectronic Materialsxe2x80x94Separate Volume (Guide Book of Apparatus for Manufacturing and Testing Super-LSIs)xe2x80x9d, pp. 121-127, issued on Nov. 18, 1986 by KK Kogyo Chosakai, or Japanese Patent Laid-Open No. 63-100746 (opened on May 2, 1988), 63xe2x80x94152150 (opened on Jun. 24, 1988) or 63-157438 (opened on Jun. 30, 1988).
First Aspect of the Present Invention
With the prior art as stated above in connection with the first aspect of the present invention, the fabrication needs to be redone from a wafer process for forming the wiring pattern anew, irrespective of whether the scale of the request for the corrections is large or small. In, for example, a large-scale logic integrated circuit device which has a multilayer wiring structure including as many as four layers, a long time is expended on the operations of the logic corrections, etc., to pose the problem that the development periods of the large-scale logic integrated circuit device and an electronic computer system employing it become long.
Moreover, the conventional wafer prober is furnished with a wafer chuck which fixes a semiconductor wafer by virtue of vacuum section. In this regard, it has the problem that, with the wafer chuck left intact, the large-scale logic integrated circuit device split into each individual chip state, for example, cannot be fixed and probed by the vacuum suction.
Further, the techniques of the aforementioned official gazette of Japanese Patent Application Laid-Open No. 116144/1985 are effective to avoid the degradations of the positioning accuracies of individual chips attendant upon the enlargement of the diameter of a semiconductor wafer. However, a dedicated test apparatus for testing the semiconductor integrated circuit device divided into the chip state must be prepared separately from the wafer prober which has hitherto been used. This incurs the drawback that a facility investment for the test process increases unreasonably.
It is therefore an object of this first aspect of the present invention to provide a technique according to which logic, functions, etc. are corrected on a finished chip by the use of FIB (Focused Ion Beam) cutting laser CVD, etc. (hereinafter, the technique shall be called xe2x80x9con-chip corrections xe2x80x9d).
A further object of the first aspect of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which is capable of shortening the development periods of the semiconductor integrated circuit device and a system employing it.
A further object of this first aspect of the present invention is to provide a method of testing a semiconductor integrated circuit device which realizes the probing of a pellet with a wafer prober and which is capable of shortening a required time and curtailing a cost in the probing of the pellet.
A still further object of this first aspect of the present invention is to provide a jig for testing a semiconductor integrated circuit device which realizes the probing of a pellet with a wafer prober and which is capable of enhancing a test accuracy and also shortening a required time and curtailing a cost in the testing process of the pellet.
A still further object of this first aspect of the present invention is to provide a method which shortens the development periods of high-degree systems (LSIs having high densities of integration and an electron device including them).
A further object of this first aspect of the present invention is to provide methods of developing, correcting and mass-producing a semiconductor integrated circuit device which are well suited to debug an electron device of complicated assemblage and installation processes.
A further object of this first aspect of the present invention is to provide a method of correcting wiring which is free from the undesirable remainder of subbing Cr (chromium), or the like.
A further object of this aspect of the present invention is to provide a method of intersecting pieces of jumper wire on a final passivation film without short-circuiting them.
A further object of this first aspect of the present invention is to provide a spare wiring layout which is well suited for on-chip wiring corrections.
A further object of this first aspect of the present invention is to provide a method of forming that recess of uneven wiring which is well suited for FIB processing effective for a notch preventive of short-circuiting in on-chip corrections.
A further object of this first aspect of the present invention is to provide a FIB processing technique which is effective for the cutting of an interconnection line, etc. in on chip-corrections.
A further object of this first aspect of the present invention is to provide developing and mass-producing methods which are suited to develop and mass-produce a custom IC (Integrated Circuit) or master slice IC having multilayer wiring.
A further object of this aspect of the present invention is to facilitate testing (probing) an IC or the like of large amount of heat production in its chip state.
Illustrative embodiments of this first aspect of the present invention are briefly summarized in the following paragraphs.
A method of manufacturing a semiconductor integrated circuit device in this first aspect of the present invention consists in that each of a plurality of articles of the identical sort of semiconductor integrated circuit device formed via a wafer process is split into individual pellets, which are thereafter assorted into a first group and a second group; that the pellets belonging to the first group are assembled into an intended system, while the pellets belonging to the second group are kept in stock; that when any functional defect has been found out in the first group of pellets assembled in the system, the second group of pellets are subjected to wiring corrections for eliminating the functional defect and are thereafter assembled into the system; and that these steps are repeated.
In addition, a method of testing a semiconductor integrated circuit device in this first aspect of the present invention consists in that a wafer prober including a wafer chuck is employed, and that a pellet is fixed to the wafer chuck while being held in a window which is provided in a part of a wafer-shaped jig, whereby the pellet is probed.
Besides, a jig for testing a semiconductor integrate circuit device in this first aspect of the present invention comprises a wafer-shaped base plate which is detachably placed on a wafer chuck of a wafer-prober, and a window which is provided in a part of the base plate and in which a pellet is located.
With the aforementioned method of manufacturing a semiconductor integrated circuit device according to this first aspect of the present invention, when a function defect has been found out in the first group of pellets assembled in the actual system, the second group of pellets already finished up are subjected to the wiring corrections for eliminating the functional defect of the first group of pellets and are thereafter exchanged for the first group of pellets, thereby making it possible to eliminate the functional defect of the first group of pellets or to take measures coping with a specification alteration etc. more promptly than in, for example, a case where a multilayer wiring structure is partly or wholly remade from the beginning by the wafer process in order to eliminate the functional defect.
Thus, the development periods of the semiconductor integrated circuit device and the system employing it can be shortened greatly.
In addition, with the aforementioned method of testing a semiconductor integrated circuit device according to this first aspect of the present invention, the semiconductor integrated circuit device in the pellet state can be probed without any remodeling of the conventional wafer prober, so that a probing apparatus dedicated to the pellet, for example, need not be prepared anew, thereby making it possible to shorten a required period of time and to curtail a cost in the process for probing the pellet.
Besides, with the aforementioned jig for testing a semiconductor integrated circuit device according to this first aspect of the present invention, the semiconductor integrated circuit device in the pellet state can be probed without any remodeling of the conventional wafer prober, so that a probing apparatus dedicated to the pellet, for example, need not be prepared anew, thereby making it possible to shorten a required period of time and to curtail a cost in the probing of the semiconductor integrated circuit device in the pellet state.
Moreover, the pellet can be positioned to the testing system stably and highly accurately, so that the test accuracy of the probing can be enhanced.
In the above prior art such as Japanese Patent Laid Open No. 106750/83, etc., regarding how to judge the time when a desired cutting depth was attained and how to stop cutting, it is merely mentioned that the radiation time and dose amount are made variable. An expression representing an etching depth S is shown on page 4 of the said laid open print, but there is no concrete description therein as to how cutting to a target depth can be done from that expression. A secondary ion analyzing method is referred to therein as a concrete method for detecting a cutting and point.
However, the LSI adopts a multilayer interconnection, so in order to cut a lower-layer wiring, it is necessary to form a hole typically having a high aspect ratio, such as a cutting area of 5 xcexcm2 and a cutting depth of 10 xcexcm, as shown in the sectional view of a cutting region of FIG. 14C. In the case of a small cutting depth, as shown in FIG. 14B, a sufficient quantity of secondary ions 29xe2x80x2 are detected by a secondary ion detector 30xe2x80x2. But at a higher aspect ratio, as in FIG. 14C, secondary ions 29xe2x80x2 are scarcely detected. By this method, therefore, it is impossible to detect a cutting end point.
On the other hand, if the beam current and the acceleration voltage are constant, the cutting depth is proportional to the cutting time. In the case of a small cutting depth, the cutting time is short, so when the depth was controlled by the cutting time on the assumption that the beam current was constant within the said time, there occurred no large error.
In the hole shown in FIG. 14C, however, about 14 minutes was required for cutting, for example, a volume of 5xc3x975xc3x9710=250 xcexcm3 at a typical cutting speed of 0.3 xcexcm3/S, and within this time it is impossible to ignore a drift of a beam current iB as shown in FIG. 14D, which drift may exceed 10%. Therefore, where a cutting time is set on the basis of an initially-set current value and thereafter a drift is made in a decreasing direction of the beam current, as shown in FIG. 14E, an actual depth becomes insufficient so it is impossible to cut a wiring 31xe2x80x2. Conversely, where a drift is made in an increasing direction of an actual current value as compared with an initially-set current value, cutting will be done to a larger depth than a target depth, reaching a lower-layer wiring, resulting in the occurrence of problems, e.g. short-circuit with an upper-layer wiring due to reattachment 33xe2x80x2 of sputter from the lower-layer wiring.
Further, it has become clear that the technique disclosed in the foregoing Japanese Patent Laid Open No. 106750/83 involves the following problem.
In the recent LSIs there is generally adopted a multilayer interconnection and the spacing between adjacent wirings in the same layer is narrow, so for cutting a wiring in an internal layer it is necessary to form a hole having a high aspect ratio of, for example, a cutting area of 5 xcexcm2 and a cutting depth of 10 xcexcm, and thus an extremely high accuracy etching is required. On the other hand, a multilayer interconnection of an LSI is formed by laminating an insulating film of for example silicon dioxide (SiO2) and a wiring of for example aluminum (Al) successively on a semiconductor of for example a silicon (Si) single crystal by vapor deposition or any other suitable method, and subjecting the layers formed to a desired etching. Thus, it is formed through such working process. In the multilayer interconnection, therefore, a positional deviation which has occurred in the LSI working process may occur between the lower wiring layer in which the cutting region is positioned and the upper layer positioned thereabove. Consequently, in the case of positioning the cutting region located in the lower layer on the basis of a positioning mark formed on the upper layer, it is impossible to make an accurate positioning of the cutting region due to the foregoing positional deviation between upper and lower layers, sometimes resulting in that it is difficult to cut the desired part. This has been made clear by the present inventors.
In a cutting work using an ion beam, as shown in the above Japanese Patent Laid Open No. 202038/83, it is important to detect charged particles or emission spectrum emitted from a workpiece in order to control the depth of a cutting region with a high accuracy.
In the above prior art, however, no consideration is given to the case where a cutting region is in the form of a relatively deep concave and it is difficult to detect charged particles such as secondary ions and secondary electrons or an emission spectrum emitted from the cutting region.
More particularly, the present inventors have found the following problem. For example, in a logical element having a multilayer interconnection structure, in the case of making a logical correction, taking measures against a defective design or making analysis of a defect by cutting and exposure of wiring using an ion beam, if the wiring is in a relatively deep position, the aspect ratio (the ratio of depth to bore) of a cut-away hole becomes large, so that charged particles such as secondary ions and secondary electrons or an emission spectrum generated at the bottom of the cut-away hole will be captured in the interior of the cut-away hole. Consequently, the detection sensitivity is deteriorated and it is difficult to make an accurate control for the cut-away hole on the basis of detected charged particles or emission spectrum from the cutting region.
Where thickness of each constituent layer of a multilayer interconnection structure is known in advance, it is possible to control the cutting depth on the basis of the cutting speed. However, the thickness of each constituent layer of a multilayer interconnection structure usually differs greatly between the interiors of the same semiconductor wafers, between discrete semiconductor wafers and between semiconductor wafers processed simultaneously, depending on variations in the manufacturing process such as deposition. It requires much labor and is actually difficult to trace the thickness of each constituent layer of a multilayer interconnection structure on each individual case.
According to studies made by the present inventors, the technique of the foregoing Japanese Patent Publication No. 6173/79 involves the problem that the diameter of the hole formed by the radiation of a laser beam is usually as small as about 5 to 10 xcexcm, while the diameter of the tip end portion of each probe is as large as about 3 xcexcm even at the smallest, so it is difficult to secure contact of the probe with the wiring. In manual probing, moreover, since the number of probes is limited, it is impossible to supply power while putting probes on all power supply pads during potential measurement. As a result, there occurs a drop in supply potential in the interior of LSI, making it impossible to measure the potential of a defective part accurately.
In the prior art disclosed in Japanese Patent Laid Open No. 106750/83, it is merely mentioned that the radiation time and dose amount are made variable regarding how to judge the time when a desired cutting depth was obtained and stop cutting. Although an expression representing an etching depth S is shown on page 4 of the said publication, there is found no concrete description therein about in what manner a target depth can be cut in accordance with the said expression. As to a concrete method for detecting a cutting end point, a method of analyzing secondary ions is mentioned therein.
However, since the LSI adopts a multilayer interconnection, in order to cut a lower-layer wiring, it is necessary to form a hole having a high aspect ratio, typically like a cutting area of 5 xcexcm2 and a cutting depth of 10 xcexcm, as shown in the section of a cutting region in FIG. 18C. In the case of a small cutting depth as shown in FIG. 18B, a sufficient amount of secondary ions 520xe2x80x2 can be detected by a secondary ion detector 521xe2x80x2. But at a high aspect ratio, as shown in FIG. 18C, the secondary ions 520xe2x80x2 are scarcely detected. With this method, therefore, it is impossible to detect a cutting end point.
On the other end, if the beam current and the acceleration voltage are constant, the cutting depth is proportional to the cutting time. In the case of a small cutting depth, the cutting time is short, so even when the depth was controlled by the cutting time on the assumption that the beam current was constant within the said time, there occurred no great error.
In the hole illustrated in FIG. 18C, however, it requires about 30 minutes to cut, for example, a volume of 5xc3x975xc3x9710=250 xcexcm3 at a typical cutting speed of 0.14 xcexcm3/S. Within this time it is impossible to ignore the drift of the beam current iB, as shown in FIG. 18D. The drift sometimes exceeds 10%. Therefore, as shown in FIG. 18E, when the cutting time is set on the basis of an initially-set current value and thereafter a drift is made in a decreasing direction of the beam current, the actual depth will be insufficient to cut a wiring 522xe2x80x2. Conversely, where a drift is made in an increasing direction of the actual current value as compared with the initial current value, even a lower-layer wiring deeper than a target depth will be cut, causing problems such as, for example, short-circuit with the upper-layer wiring due to reattachment of sputter 524xe2x80x2 from the lower-layer wiring.
It is an object of the second aspect of the present invention to control a cutting depth with a high accuracy even when the beam current changes during the cutting.
It is another object of this second aspect of the present invention to provide a technique capable of radiating an ion beam to a desired position of a workpiece to effect an exact cutting of high accuracy.
It is a further object of this second aspect of the present invention to provide a semiconductor device having a hole of a high aspect ratio formed at an accurate depth as well as a cutting technique using an ion beam capable of controlling a cutting depth with a high accuracy.
It is a still further object of this second aspect of the present invention to provide a technique capable of accurately measuring the potential of an internal circuitry of a semiconductor integrated circuit device.
It is a still further object of the second aspect of the present invention to monitor the cutting depth with a high accuracy even when the beam current changes during cutting.
The foregoing objects are attained by measuring a beam current at very short time intervals during cutting of a single hole, integrating the product of the thus-measured value and a cutting rate coefficient with respect to time to obtain a cut-away volume, and dividing the latter by the area of a beam scan region.
The above and other objects as well as novel features of this aspect of the present invention will become apparent from the following description and the accompanying drawings.
Typical inventions disclosed herein will be outlined below.
The foregoing first object is attained by measuring a beam current at very short time intervals during cutting, integrating the measured value with respect to the time to obtain a radiation ion quantity (hereinafter referred to as xe2x80x9cdose amountxe2x80x9d) and calculating a cutting depth using the dose amount.
The second invention disclosed, herein will be typically outlined below.
In cutting a cutting region by radiating an ion beam to the same region which is positioned in an internal layer of a predetermined depth of a sample, an ion beam radiating position is determined by reference to a cutting reference mark formed at a depth equal to or approximately equal to the depth of the cutting region and there is performed cutting of the same region.
The third invention disclosed herein will be typically outlined below.
In a semiconductor device there is provided a trial cutting region equal in structure in the depth direction and in formation history to an element region.
Further, there are provided an ion source; an ion beam optical system for controlling the acceleration of an ion beam emitted from the ion source and also controlling an arrival position of the beam relative to a workpiece; a detecting means for detecting charged particles or emission spectrum emitted from a cutting region of the workpiece; an ion beam current measuring means for measuring an ion beam current; a dose amount calculating section for measuring a time required for cutting in each of the constituent layers of the workpiece on the basis of changes in charged particles or emission spectrum emitted from the workpiece and integrating the ion beam current measured during cutting of each layer in accordance with the said required time to thereby calculate a dose amount required for cutting per unit area of each layer in the workpiece; and a dose amount storage section for storing the calculated dose amount required for cutting per unit area of each layer, wherein the cutting of a second region is carried out through first and second stages. In the first stage, the dose amount required for cutting per unit area of each layer in a first region of the workpiece is grasped and stored in the dose amount storage section, while in the second stage, a target dose amount required for cutting up to a desired depth in the second region of the workpiece is set on the basis of the dose amount required for cutting per unit area of each layer in the first region of the workpiece which has been stored in the dose amount storage section, and cutting is performed until a dose amount obtained by integrating an ion beam current during cutting with respect to time reaches a target dose amount.
The fourth invention disclosed herein is typically outlined that it is provided with auxiliary bumps or pads in a floating state.
The operation of the first invention is as follows.
In a cutting work using a focused ion beam, as shown in FIG. 13F, atoms 34xe2x80x2 sputtered by an ion beam 28xe2x80x2 reattaches to the side rail of a cut-sway bolt to form a reattachment layer 35xe2x80x2 so that the side rail of the cut-away hole is inclined. A change in shape of the cut-away hole formed by the reattachment layer exerts an influence on the cutting speed for the depth.
As a result of experiments we obtained such a relationship as shown in FIG. 13G. Where a cutting width L is sufficiently large (4d or more) relative to a value, 2d, twice a beam diameter,d, cutting is started, and while a flat portion remains on the bottom of a cut-away hole, cutting depth Z is proportional to a dose amount D. With further advancement of cutting, when the flat portion of the cut bottom disappears due to reattachment of sputter and the cut-away hole becomes wedge-like, the cutting speed for the cutting depth Z becomes lower as shown in FIG. 13G. Where the cutting width L is narrower than the above, that is, where L is about the same as or smaller than twice the beam diameter, d, Z and D do not exhibit a proportional relation from the cutting start point, so the advancing speed of Z becomes lower with progress of cutting. In view of this point we have invented depth controlling methods with respect to both the case where Z is proportional to D and the case where Z is not proportional to D.
Where Z is proportional to D, a beam current is measured at a very short time interval during cutting and the measured value is integrated with respect to time to obtain a dose amount D, which in turn is multiplied by a constant of proportion to determine a depth Z. It is here assumed that the sputter volume per unit incident ion quantity of a workpiece; material M is kM[xcexcm3/nc] (hereinafter referred to as the xe2x80x9ccutting rate coefficient of material Mxe2x80x9d) and the opening area at the start of cutting is A [xcexcm2](A=L1xc3x97L2, L1 and L2 being longitudinal and transverse widths, respectively). The cutting depth Z is obtained by dividing the volume V (hereinafter referred to as xe2x80x9csputter volumexe2x80x9d) of the cut-away hale which is in the form of a rectangular parallelopiped, by an opening area A, ignoring reattachment and assuming that all the sputter atoms disappear. Therefore, the following equations are established:
V=kMDxe2x80x83xe2x80x83(1)
                    Z        =                              V            /            A                    =                                    kM              A                        ⁢            D                                              (        2        )            
Thus, the constant of proportion of the above Z and D becomes       kM    A    .
Next, where Z and D are not proportional to each other, the dose amount D is determined in the same manner as above. Thereafter, the depth Z is determined using a cutting depth function Z=g(D) which has been obtained beforehand by a trial cutting experiment.
According to the foregoing second invention, it is possible to effect cutting with an ion beam in an exact position since an ion beam radiating position can be determined by reference to a cutting reference mark formed with a view to serving as a reference in positioning a cutting region.
According to the foregoing third invention, a trial cutting is performed in a trial cutting region in performing an ion beam cutting with a view to making logical correction, taking measures against a defective design or making analysis of a defect, whereby a dose amount per wait area of each layer can be grasped accurately is advance and it is possible to form a hole of a high aspect ratio at an exact depth in an element region.
For example, is cutting a second region of a workpiece, even when the cutting region is the form of a concave of a high aspect ratio having a large depth as compared with a cutting area and it is difficult to control the cutting depth under changes is the amount of secondary ions or secondary electrons emitted from the cutting region and detected, it is possible to set as exact target dose amount according to the cutting depth for the second cutting region on the basis of a dose amount per unit area of each layer which has already been grasped in the cutting of the first cutting region and stored in the dose amount storage section. The cutting depth can be controlled precisely by monitoring a dose amount which is obtained by integrating an ion beam current with respect to a cutting time.
According to the foregoing fourth invention, it is possible to make a potential measurement by connecting a portion to be measured for potential with an auxiliary bump or pad through wiring, thus permitting as exact potential measurement for an internal circuitry.
Further, the cutting depth can be monitored with a high accuracy even upon change in beam current during cutting, by measuring a beam current at a very short time interval during cutting for a single hole, then integrating the product of the measured value and a cutting rate coefficient with respect to time to obtain a cut-away volume and dividing the latter by the area of a beam scan region to obtain a cutting depth. More specifically, in a cutting rock using an ion beam, since a sample is cut by sputtering, sputter particles 525 are more likely to reattach to the side rail of a cut-away hole as the bole becomes deeper as shown in FIG. 17F, resulting is that the hole becomes tapered. Therefore, the opening portion comes to have an area A same as that of the beam scan region, but as the hole becomes deeper, a bottom area Axe2x80x2 becomes smaller than the area A.
As a result of an experiment it wan confirmed that a cut-away hole volume gradually decreased in its rate of increase with respect to the cutting time (the beam current can be regarded as being almost constant), as shown is FIG. 17G. But the cutting depth increases at a constant rate of increase as long as the flat portion remains on the bottom (Axe2x80x2 greater than 0) as shown in FIG. 17H. It became clear, however, that this relation was no longer valid when the hole became conical with no bottom surface (Axe2x80x2=0).
Therefore, as shown is FIG. 17H, it is presumed that the volume V of the material sputtered by beam is constant with respect to time, but the reattachment volume V2 increases as the hole becomes deeper, so the rate of increase of the cut-away hole volume V1=Vxe2x88x92V2 changes. The volume V of the material sputtered with beam is referred to herein as a cut-away volume V. The cut-away volume V is represented as follows:
V=9∫kiBdt
where
k: cutting rate coefficient [xcexcm3Axe2x88x921 secxe2x88x921]
iB: beam current [A]
This volume corresponds to a cut-away hole volume in the absence of reattachment of sputter particles and is therefore the volume of a quadrangular prism free of tape: wherein the sectional area is A (the area of the beam scan region) everywhere.
Therefore, the cutting depth Z can be determined as follows:
z=V/A.
The prior arts discussed above in connection with the third aspect of the present invention suffer from the following problems.
The techniques proposed in Japanese Patent Application No. 70979/1986 has the problems that photolithography and etching steps are needed to form an insulating film only in the vicinities of contact holes and that the process for preventing shorting between the wirings in the first- and second-level layers is complicated.
In the first prior art, a means for disconnecting wirings alone is shown but no means for reconnecting the wirings is shown. Further, employment of a laser machining method involves the following disadvantages:
(1) Since the machining process is thermally executed, conductive of heat to the surroundings is unavoidable, and since processes such as evaporation and blowoff of vapors take place, it is extremely difficult to conduct a fine machining operation on the order of 1.5 xcexcm or less.
(2) Laser light is only slightly absorbed by insulating films such as SiO2, Si3N4 or the like and it is therefore absorbed by an aluminum or polysilicon wiring to the underlayer, and when such a wiring evaporates and blows off, it explosively blows the upper insulating film away, thereby effecting machining of the insulating film. For this reason, when the thickness of the insulating layer is 2 xcexcm or more, it is difficult to machine the insulating film. Further, the peripheral portions (the surroundings and the upper and lower layers) are greatly damaged, and this leads to generation of defects. These results show that it is difficult to machine wirings in ICs having a multilayer wiring structure or a high degree of integration and miniaturization by the laser machining method.
The second prior art discloses (3) a means for disconnecting and boring by a focused ion beam, and (4) a means for interconnecting the upper and lower wirings by the use of a focused ion beam. Since employment of a focused ion beam enables machining on the order of 0.5 xcexcm or less and permits any materials to be successively machined from the upper layer with ease by means of sputtering, the second prior art overcomes the problems of the first prior art. However, as to the means for interconnecting the upper and lower wirings mentioned in (4), the second prior art shows only the procedure of interconnection of the upper and lower airings but does not mention any moans for providing connection between one wiring and another wiring.
The third prior art discloses a method wherein the surface of a silicon (Si) substrate coated with SiO2 is irradiated with an ultraviolet laser in a gas of a metal organic compound, e.q., molybdenum carbonyl [Mo(CO)6]to decompose Mo(CO)6 by a photothermal or photochemical laser induced CVD process, thereby depositing a metal, e.q., molybdenum (Mo) on the substrate and thus lithographically forming a metal wiring directly on the substrate. However, this prior art discloses merely a means for forming a Mo wiring on an insulating film but shows no means for interconnecting wirings which are located under an insulating film such as a protective film or an intermediate insulating film in an actual IC without any fear of these wirings shorting to a wiring disposed in an upper-level layer.
Accordingly, it is an object of this third aspect of the present invention to provide a semiconductor integrated circuit device which is so designed that it is possible to form a connecting wiring without causing shorting between wirings respectively located in lower and upper level layers in a multilayer wiring structure.
It is another object of this third aspect of the present invention to provide a process for producing a semiconductor integrated circuit device which enables formation of a simple connecting wiring for interconnecting wirings respectively located in lower- and upper-level layers in a multilayer wiring structure.
It is still another object of this third aspect of the present invention to provide an IC which is so designed that it is possible to form tins holes in an insulating film such as a protective film or an intermediate insulating film in the IC, thereby enabling a wiring located under an insulating film such as a protective film or an intermediate insulating film to be connected to another portion through a connecting wiring and thus permitting the IC to be subjected to debugging, repair, a defect analysis, etc., and also provide a method of interconnecting wirings in the IC.
According to a fourth aspect of the present invention, we have investigated the logic correcting technique using the aforementioned focused ion beam and laser CVD to find the following problems:
The formation of the conductive pattern with the laser CVD makes use of the thermal reactions due to the temperature rise at the laser-irradiated portion. If the wafer surface is irradiated with the laser beam, the temperature rises at the irradiated portion of the insulating film so that the reactive gases such as W(CO6) or Mo(CO6) are decomposed to deposit the conductive film of W or Mo selectively over the insulating film at the portions irradiated with the laser beam. If, therefore, the wafer or laser beam is moved in a predetermined direction with the wafer surface being irradiated with the laser beam, the conductive pattern can be foamed along the moving locus.
If, however, the surface of the insulating film is irradiated with the laser beam, the temperature of the insulating film not only at the irradiated portion but also in its neighborhood is raised by the heat conduction of the insulating film so that the width of the conductive pattern obtained extends as wide as 5 xcexcm even if the spot size of the laser beam is focused to about 2 xcexcm.
On the other hand, the width of the conductive pattern obtained may be different between the cases, in which the insulating film at the portions irradiated with the laser beam is underlaid by the wiring and not, even if the laser beam has a predetermined spot size. In the portion having the underlying wiring, more specifically, the heat of the insulating film will be promptly transferred to the underlying wiring so that the temperature of the insulating film will not rise so much. On the contrary, the temperature of the insulating film is liable to rise in the portion having no underlying wiring. As a result, the width of the conductive pattern becomes larger in the portion having no underlying wiring than that of the other portion.
Thus, in the conductive pattern-forcing technique using the laser CVD, the width of the conductive pattern obtained may be wider than necessary or may disperse. This raises a problem that the adjacent conductive patterns are short-circuited if the conductive patterns are to be arranged in the vicinity.
This fourth aspect of the present invention has been conceived in view of the problems described above, and has an object to provide a technique capable of effectively preventing the short-circuiting of conductive patterns arranged adjacent to each other when the connections of wirings are to be corrected by using the focused ion beam and the laser CVD.
One object of this fourth aspect of the present invention is to provide a technique for correcting the logic or function on a completed chip by using the FIB (Focused Ion Beam) cutting and the laser CVD (as will be shortly referred to as xe2x80x9con-chip correctionxe2x80x9d).
A further object of this fourth aspect of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device within a short period for developing the semiconductor integrated circuit device and a system using the former.
A further object of this fourth aspect of the present invention is to provide a method of shortening the period for developing a high-grade system (such as an LSI having a high degree of integration and an electronic device composed of the LSI).
A further object of this fourth aspect of the present invention is to provide a method of developing, correcting and mass-producing a semiconductor integrated circuit device which is suitable for debugging or adjusting (or functionally testing) an electronic device having complicated assembling and installing steps.
A further object of this fourth aspect of the present invention is to provide a wiring correcting method which is clear at any undesirable underlying barrier metal such as Cr.
A further object of this fourth aspect of the present invention is to provide an FIB processing technique which is effective for cutting the mutual wirings of on-chip correction.
A further object of this fourth aspect of the present invention is to provide a developing and mass-producing method which is suitable for developing a custom IC, (Integrated Circuit) having multilayer wirings and a master slice IC,
A further object of this fourth aspect of the present invention is to improve the reliability of the wiring corrections with the laser beam, firstly be preventing the wiring of deposited film formed on a sample surface from being cracked and secondly by ensuring the terminal detection at the deposition of the metal layer in the through holes to prevent the boundary between the load-out wiring portion and the aforementioned wiring from being cracked.
A further object of this fourth aspect of the present invention is to provide a semiconductor device technique which can facilitate the correctional processing operations of the wirings, simplify the wiring correctional processing system and improve the yield of the wiring correctional processing.
A further object of this fourth aspect of the present invention is to provide a technique capable of improving the throughput of the logic correcting step using the FIB and the laser CVD.
Another object of this fourth aspect of the present invention is to provide a technique which can achieve the objects described above and can improve the yield of the logic correcting step using the FIB and the laser CVD.
Still another object of this fourth aspect of the present invention is to provide a technique which can achieve the objects described above and can effectively prevent a drop in resistance to electro-migration of the power source wiring.
A further object of this fourth aspect of the present invention is to provide a technique capable of achieving the objects described above, and also promote automation of the logic correcting step using the FIB and the laser CVD.
Another object of this fourth aspect of the present invention is to provide a technique capable of reliably preventing short-circuiting in the wiring corrections of the first and second wiring structures to be laminated through a second insulating film.
A further object of this fourth aspect of the present invention is to provide a semiconductor integrated circuit device which is reliably feed from the short-circuiting in the wiring correction of the first and second wiring structures to be laminated through a second insulating film.
A further object of this fourth aspect of the present invention is to provide a wiring correcting method capable of reliably preventing short-circuiting in the wiring correction of the first and second wiring structures to be laminated through a second insulating film.
A further object of this fourth aspect of the present invention is to provide a method of developing a main frame computer which can shorten the developing period by constructing a semiconductor integrated circuit device and by reliably preventing short-circuiting in the wiring correction of the lust and second wiring structures to be laminated through a second insulating film.
A representative example of the inventions to be disclosed hereinafter will be summarized in the following.
According to this fourth aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of: etching a passivation film of an integrated circuit formed over a wafer with a focused ion beam to expose a wiring to the outside at its pardon to be cut away; cutting the wiring with the focused ion beam; selectively coating by laser CVD a wide conductive pattern between the wirings to be connected; and etching said wide conductive pattern with said focused ion beam thereby to form a plurality of narrow conductive patterns.
According to the means specified above, the wide conductive pattern having been formed with the laser CVD is etched with a focused ion beam to form a plurality of narrow conductive patterns. This makes it possible to the adjacent conductive patterns form being short-circuited even if the conductive patterns are eider than necessary when the wide conductive pattern is formed with the laser CVD.